The present invention relates to a clock synchronizer, and particularly, to a clock synchronizer generating a second clock signal synchronized with a first clock signal.
Conventionally, a semiconductor integrated circuit device is provided with a PLL (Phase Locked Loop) circuit generating an internal clock signal in synchronization with an external clock signal in order to synchronize the outside and the inside of a chip.
FIG. 23 is a circuit block diagram showing the configuration of such a PLL circuit. In FIG. 23, the PLL circuit includes a phase comparator 121, a charge pump circuit 122, a loop filter 127, a voltage control oscillator (hereinafter referred to as VCO) 130, and a frequency divider 131.
An external clock signal is input into phase comparator 121 as a reference clock signal RCLK. Phase comparator 121 compares the phase of reference clock signal RCLK and that of a feedback clock signal FCLK, and outputs signals UP, DOWN based on the comparison result. When the phase of clock signal FCLK is advanced with respect to the phase of reference clock signal RCLK, signal DOWN is raised to an activated level of xe2x80x9cHxe2x80x9d level for a time period corresponding to a phase difference, and when the phase of clock signal FCLK is delayed with respect to the phase of reference clock signal RCLK, signal UP is lowered to an activated level of xe2x80x9cLxe2x80x9d level for a time period corresponding to a phase difference. When there is no difference in the phases of clock signals FCLK and RCLK, signals DOWN, UP are set to be at xe2x80x9cHxe2x80x9d level and xe2x80x9cLxe2x80x9d level, respectively, in a pulsive manner.
Charge pump circuit 122 includes a P-channel MOS transistor 123 and a switching element 124 connected in series between the line of a power-supply potential VCC and a node N122; and a switching element 125 and an N-channel MOS transistor 126 connected in series between node N122 and the line of a ground potential GND.
The gate of P-channel MOS transistor 123 is supplied with a constant bias potential VBP, whereas the gate of N-channel MOS transistor 126 is supplied with a constant bias potential VBN. Each of MOS transistors 123, 126 constitutes a constant-current source. Switching element 124 conducts for a period during which signal UP is at the activated level of xe2x80x9cLxe2x80x9d level. Switching element 125 conducts for a period during which signal DOWN is at the activated level of xe2x80x9cHxe2x80x9d level.
Loop filter 127 includes a resistance element 128 and a capacitor 129 connected in series between node N122 and ground potential GND. Capacitor 129 is charged and discharged by charge pump circuit 122. The voltage of node N122 is supplied to VCO 130 as a control voltage VC.
VCO 130 outputs an internal dock signal CLK having a frequency corresponding to control voltage VC. Internal clock signal CLK is applied to an internal circuit of the semiconductor integrated circuit device and also to frequency divider 131. Frequency divider 131 divides the frequency of clock signal CLK by N (wherein N is a positive integer) to generate clock signal FCLK. Clock signal FCLK is returned to phase comparator 121.
Control voltage VC is adjusted such that the frequencies and phases of clock signals RCLK and FCLK agree with each other, and then the frequencies and phases of clock signals RCLK and FCLK agree with each other, resulting in a lock state. In the locked state, internal clock signal CLK has a frequency N times as high as that of external clock signal RCLK and is a signal synchronizing with external clock signal RCLK. The internal circuit of the semiconductor integrated circuit device operates in synchronization with internal clock signal CLK. Therefore, the outside and the inside of the chip can be synchronized.
However, the conventional PLL circuit had problems as described below.
Now, a case is considered where reference clock signal RCLK and feedback clock signal FCLK agree in phase. In this case, signal UP is lowered to xe2x80x9cLxe2x80x9d level in a pulsive manner for a certain period of time with the same cycle as that of dock signals RCLK, FCLK. Likewise, signal DOWN is raised to xe2x80x9cHxe2x80x9d level in a pulsive manner for the same period of time and with the same cycle as that of signal UP. The reason why signals UP, DOWN are set to be at xe2x80x9cLxe2x80x9d level and xe2x80x9cHxe2x80x9d level in a pulsive manner even though clock signals RCLK and FCLK agree in phase with each other is to avoid a dead band being created.
At this moment, if current Ic flowing through P-channel MOS transistor 123 is the same as current Id flowing through N-channel MOS transistor 126, signals UP and DOWN will have the same pulse width, so that the exactly same amount of charge is charged and discharged without the amount of charge in capacitor 129 of loop filter 127 changed. Thus, no change occurs in control voltage VC, and VCO 130 keeps outputting clock signal CLK having the same frequency X (Hz). As a result, the PLL circuit will be in the locked state in a state having no phase difference between clock signals RCLK and FCLK.
However, when there is no agreement between charging current Ic and discharging current Id, the locked state cannot be obtained in the state having no phase difference between clock signals RCLK and FCLK. For example, considering the case where charging current Ic is larger than discharging current Id, if signals UP and DOWN have the same pulse width, the amount of charge that is charged by charging current Ic will be unequal to the amount of charge that is discharged by discharging current Id. To equalize these amount of charges, the pulse width of signal DOWN must be made larger than the pulse width of signal UP.
Then, the state where the pulse width of signal DOWN is larger than the pulse width of signal UP means a state where the phase of feedback clock signal FCLK is delayed with respect to the phase of reference clock signal RCLK, and the PLL circuit is locked in this state. This generates a steady phase difference, i.e. an offset, between clock signals RCLK and FCLK. Same applies to the case where discharging current Id is larger than charging current Ic. In sum, in the PLL circuit, if there is no agreement in magnitude between charging current Ic and discharging current Id, an offset will occur.
Next, a case is considered where charging current Ic and discharging current Id disagree with each other in magnitude. In designing of the PLL circuit, assuming that the operating frequency of the PLL circuit is X (Hz), VCO 130 obtains a control voltage Y (V) oscillated at X (Hz), and the sizes of MOS transistors 123, 126 and the levels of bias potentials VBP, VBN are determined such that charging current Ic and discharging current Id are equal to each other when control voltage VC is Y (V). Therefore, when the PLL circuit operates as designed, charging current Ic and discharging current Id are equal to each other, and hence the locked state is attained in the state having no phase difference between clock signals RCLK and FCLK.
However, due to variations of a manufacturing process, an environment temperature and power-supply voltage VCC, control voltage VC at the time when output clock signal CLK of VCO 130 attains to X (Hz) is easily varied from Y (V). Moreover, when the PLL circuit is operated at a frequency other than X (Hz), control voltage VC in the locked state is a value different from Y (V). Therefore, in such cases, charging current Ic and discharging current Id are unequal, and an offset occurs.
Therefore, a main object of the present invention is to provide a clock synchronizer capable of inhibiting occurrence of an offset.
An object of the present invention can be achieved by providing a clock synchronizer generating a second clock signal synchronized with a first clock signal, including a phase difference detection circuit detecting a phase difference between the first and second dock signals, and setting a first control signal to be at an activated level for a time period corresponding to the phase difference; a loop filter connected to a predetermined node; a current-supply circuit supplying current to the loop filter in response to the first control signal from the phase difference detection circuit; and a clock generating circuit generating the second dock signal in accordance with a potential of the predetermined node. The current-supply circuit includes a variable current source whose output current can be controlled, a first switching circuit passing output current of the variable current source through the loop filter in response to that the first signal is set to be at the activated level, and a first control circuit: controlling the variable current source such that predetermined constant current flows from the variable current source to the loop filter, based on the potential of the predetermined node.
A main advantage of the present invention is that the variable current source is controlled such that constant current flows from the variable current source to the loop filter, based on the potential of the predetermined node, so that constant current can flow from the variable current source to the loop filter even when the potential of the predetermined node is varied, and thus occurrence of an offset can be inhibited.
Preferably, the variable current source includes a first transistor of a first conductivity type whose input electrode receives a first control potential. The first switching circuit connects the first transistor between a line of a first power-supply potential and the loop filter in response to that the first control signal is set to be at the activated level, and the first control circuit controls the first control potential such that predetermined constant current flows through the first transistor connected between the line of the first power-supply potential and the loop filter, based on the potential of the predetermined node. In this case, the potential of the input electrode of the first transistor is controlled such that constant current flows through the first transistor, based on the potential of the predetermined node, so that constant current can flow through the first transistor even when the potential of the predetermined node is varied, and thus occurrence of the offset can be inhibited.
More preferably, the first control circuit includes a second transistor of a first conductivity type whose first electrode is connected to the line of the first power-supply potential, and whose input electrode is connected to a second electrode of the second transistor, and outputting the first control potential from the second electrode; a third transistor of a second conductivity type whose first electrode is connected to a second electrode of the second transistor and whose input electrode receives the potential of the predetermined node; and a first resistance element connected between a second electrode of the third transistor and a line of a second power-supply potential. This facilitates constitution of the first control circuit.
More preferably, the first control circuit further includes a second resistance element connected between the second electrode of the second transistor and the line of the second power-supply potential. In this case, even when the potential of the predetermined node is set as the second power-supply potential and the third transistor is rendered non-conductive, current can flow through the first and second transistors, and thus the current-supply circuit can be prevented from being inoperative.
More preferably, the variable current source further includes a fourth transistor of a first conductivity type, connected in parallel with the first transistor, whose input electrode receives a constant bias potential. In this case, even when the potential of the predetermined node is set as the second power-supply potential and the third transistor is rendered non-conductive, current can flow through the fourth transistor, and thus the current-supply circuit can be prevented from being inoperative.
More preferably, the clock synchronizer includes a lock detection circuit detecting whether or not the phase difference between the first and second clock signals is smaller than a predetermined level, setting a lock detection signal to be at an activated level when it is smaller, and setting the lock detection signal to be at an inactivated level when it is larger. The variable current source further includes a second transistor of a first conductivity type whose input electrode receives a constant bias potential. The first switching circuit connects the first transistor between the line of the first power-supply potential and the loop filter when the lock detection signal is at an activated level, and connecting the second transistor between the line of the first power-supply potential and the loop filter when the lock detection signal is at an inactivated level, in response to that the first control signal is set to be at an activated level. In this case, the second transistor through which current flows in accordance with the potential of the predetermined node is used when not in the locked state, whereas the first transistor through which constant current flows irrespective of the potential of the predetermined node is used when in the locked state, so that the lock-in time is made shorter compared to the case where only the first transistor is used.
More preferably, the clock synchronizer further includes a lock detection circuit detecting whether or not the phase difference between the first and second clock signals is smaller than a predetermined level, setting a lock detection signal to be at an activated level when it is smaller, and setting the lock detection signal to be at an inactivated level when it is larger. The variable current source further includes a second transistor of a first conductivity type whose input electrode receives a second control potential. The first switching circuit connects the first transistor between the line of the first power-supply potential and the loop filter when the lock detection signal is at an activated level, and connecting the second transistor between the line of the first power-supply potential and the loop filter when the lock detection signal is at an inactivated level, in response to that the first control signal is set to be at an activated level. The current-supply circuit further includes a second control circuit controlling the second control potential such that current flowing through the second transistor connected between the line of the first power-supply potential and the loop filter is increased in accordance with a potential difference between the first power-supply potential and a potential of the predetermined node, based on the potential of the predetermined node. In this case, the second transistor through which current flows in accordance with the potential difference between the first power-supply potential and the potential of the predetermined node is used when not in the locked state, whereas the first transistor through which constant current flows irrespective of the potential of the predetermined node is used when in the locked state, so that the lock-in time is made shorter compared to the case where only the first transistor is used.
More preferably, the first control signal is a signal for advancing a phase of the second clock signal. The phase difference detection circuit sets the first control signal to be at an activated level for a time period corresponding to a phase difference between the first and second clock signals when the phase of the second clock signal is delayed with respect to the first clock signal, sets a second control signal for delaying the phase of the second clock signal to be at an activated level for a time period corresponding to a phase difference between the first and second dock signals when the phase of the second clock signal is advanced with respect to the first clock signal, and sets the first and second control signals to be at an activated level for a predetermined period of time when phases of the first and second dock signals agree with each other. The current-supply circuit supplies current of a first polarity to the loop filter in response to that the first control signal is set to be at an activated level, and also supplies current of a second polarity to the loop filter in response to that the second control signal is set to be at an activated level. In this case, the phase of the second clock signal can be advanced by the first control signal, and the phase of the second clock signal can be delayed by the second control signal.
More preferably, the variable current source further includes a second transistor of a second conductivity type whose input electrode receives a second control potential. The current-supply circuit includes a second switching circuit connecting the second transistor between the loop filter and the line of the second power-supply potential in response to that the second control signal is set to be at an activated level; and a second control circuit controlling the second control potential such that the predetermined constant current flows through the second transistor connected between the loop filter and the line of the second power-supply potential, based on a potential of the predetermined node. In this case, even when the potential of the predetermined node is varied, current of the first polarity and the current of the second polarity supplied from the current-supply circuit to the loop filter may be equalized, and thus occurrence of an offset can be prevented.
Preferably, the clock synchronizer further includes a precharge circuit precharging the predetermined node to be at a predetermined potential in response to application of the first and second power-supply potentials. In this case, the time period from power-up to lock-in can be shortened.
More preferably, the current-supply circuit further includes a second transistor of a second conductivity type whose input electrode receives a constant bias potential, and a second switching circuit connecting the second transistor between the loop filter and the line of the second power-supply potential in response to that the second control signal is set to be at an activated level. In this case, though current flowing through the second transistor varies in accordance with the potential of the predetermined node, current flowing through the first transistor is maintained to be constant, not depending on the potential of the predetermined node, so that occurrence of an offset can be inhibited.
More preferably, the clock synchronizer further includes a precharge circuit precharging the predetermined node to be at the first power-supply potential in response to application of the first and second power-supply potentials. In this case, the time period from power-up to lock-in can be shortened.
More preferably, the first control signal is a signal for delaying the phase of the second clock signal. The phase difference detection circuit sets the first control signal to be at an activated level for a time period corresponding to a phase difference between the first and second clock signals when the phase of the second clock signal is advanced with respect to the first clock signal, sets a second control signal for advancing the phase of the second clock signal to be at an activated level for a time period corresponding to a phase difference between the first and second clock signals when the phase of the second clock signal is delayed with respect to the first clock signal, and sets the first and second control signals to be at an activated level for a predetermined period of time when the phases of the first and second clock signals agree with each other. The current-supply circuit supplies current of a first polarity to the loop filter in response to that the first control signal is set to be at an activated level, and also supplies current of a second polarity to the loop filter in response to that the second control signal is set to be at an activated level. In this case, the phase of the second clock signal can be delayed by the first control signal, and the phase of the second clock signal can be advanced by the second control signal.
More preferably, the current-supply circuit further includes a second transistor of a second conductivity type whose input electrode receives a constant bias potential, and a second switching circuit connecting the second transistor between the loop filter and the line of the second power-supply potential, in response to that the second control signal is set to be at an activated level. In this case, though current flowing through the second transistor varies in accordance with the potential of the predetermined node, current flowing through the first transistor is maintained to the constant, not depending on the potential of the predetermined node, so that occurrence of the offset can be inhibited.
More preferably, the clock synchronizer further includes a precharge circuit precharging the predetermined node to be at the first power-supply potential in response to application of the first and second power-supply potentials. In this case, the time period from power-up to lock-in can be shortened.
More preferably, the variable current source includes a variable potential source whose output potential can be controlled, and a transistor whose input electrode receives a constant bias potential. The first switching circuit connects the transistor between an output node of the variable potential source and the loop filter, in response to that the first control signal is set to be at an activated level. The first control circuit controls the variable potential source such that predetermined constant current flows through the transistor connected between the output node of the variable potential source and the loop filter, based on a potential of the predetermined node. In this case, the variable potential source is controlled such that constant current flows through the transistor, based on the potential of the predetermined node, so that constant current can flow through the transistor even when the potential of the predetermined node is varied, and thus occurrence of an offset can be prevented.
More preferably, the variable current source includes a variable potential source whose output potential can be controlled, and a transistor whose in put electrode receives a constant control potential. The first switching circuit connects the transistor between an output node of the variable potential source and the loop filter in response to that the first control signal is set to be at an activated level. The first control circuit controls the control potential and the variable potential source such that predetermined constant current flows through the transistor connected between the output node of the variable potential source and the loop filter, based on a potential of the predetermined node. In this case, the control potential and the variable potential source are controlled such that constant current flows through the transistor, based on the potential of the predetermined node, so that constant current can flow through the transistor even when the potential of the predetermined node is varied, and thus occurrence of an offset can be inhibited.
More preferably, the loop filter includes a resistance element and a capacitor connected in series between the predetermined node and a line of a reference potential. In this case, charge applied from the current-supply circuit to the loop filter is charged to the capacitor.
An object of the present invention is also achieved by providing a clock synchronizer generating a second clock signal synchronized with a first clock signal, including a phase difference detection circuit detecting a phase difference between the first and second clock signals and setting a control signal to be at an activated level for a time period corresponding to the phase difference; a loop filter connected to a predetermined node; a current-supply circuit supplying current to the loop filter in response to a control signal from the phase difference detection circuit; and a clock generating circuit generating the second dock signal in accordance with a control potential. The current-supply circuit includes a transistor whose input electrode receives the control potential, a switching circuit connecting the transistor between a line of a power-supply potential and the loop filter, in response to that the control signal is set to be at an activated level, and a control circuit controlling the control potential such that predetermined constant current flows through the transistor connected between the line of the power-supply potential and the loop filter, based on a potential of the predetermined node.
In this case, the control potential is controlled such that constant current flows through the transistor, based on the potential of the predetermined node, so that constant current can flow through the transistor even when the output potential of the predetermined node is varied, and thus occurrence of an offset can be inhibited. Moreover, the control potential is also used for generating the second clock signal, so that circuit configuration may be simplified.
An object of the present invention is further achieved by providing a clock synchronizer generating a second dock signal synchronized with a first clock signal, including a phase difference detection circuit detecting a phase difference between the first and second clock signals, and setting a control signal to be at an activated level for a time period corresponding to the phase difference; a loop filter including a resistance element and a capacitor connected in series between a predetermined node and a line of a reference potential; a current-supply circuit supplying current to the loop filter in response to a control signal from the phase difference detection circuit; and a clock generating circuit generating the second clock signal in accordance with a potential of the predetermined node. The current-supply circuit includes a transistor whose input electrode receives a control potential, a switching circuit connecting the transistor between a line of a power-supply potential and the loop filter, in response to that the control signal is set to be at an activated level, and a control circuit controlling the control potential such that predetermined constant current flows through the transistor connected between the line of the power-supply potential and the loop filter, based on a potential of a node between the resistance element and a capacitor.
In this case, the control potential is controlled such that constant current flows through the transistor, based on the potential of a node between the resistance element and the capacitor of the loop filter, so that constant current can flow through the transistor even when the potential of the predetermined node is varied, and thus occurrence of an offset can be inhibited.